In this paper a new Context-Adaptive Variable Length Coding (CAVLC) encoder architecture is proposed aimed to be implemented in embedded systems and field programmable logic. The design proposes novel Arithmetic Table Elimination (ATE) techniques, along with a table compression technique applied to those tables that cannot be eliminated by arithmetic manipulations. These approaches allows to halve the total number of tables requested by CAVLC algorithm and bring to an overall memory saving of about 87% with respect to an unoptimized implementation of the tables. Computational performances of the encoder have been improved by increasing the degree of parallelism through the use of priority cascading logic. With the proposed approaches the CAVLC encoder is capable of real time compression of 1080p HDTV video streams, coded in YCbCr 4:2:0, when it is implemented with a low-end Xilinx Spartan 3 FPGA, where the encoder achieves an operation frequency of 63MHz and requires an area occupancy of 2200 LUTs.
An Area Reduced Design of the Context-Adaptive Variable-Length Encoder Suitable for Embedded Systems
LICCIARDO, GIAN DOMENICO;
2010-01-01
Abstract
In this paper a new Context-Adaptive Variable Length Coding (CAVLC) encoder architecture is proposed aimed to be implemented in embedded systems and field programmable logic. The design proposes novel Arithmetic Table Elimination (ATE) techniques, along with a table compression technique applied to those tables that cannot be eliminated by arithmetic manipulations. These approaches allows to halve the total number of tables requested by CAVLC algorithm and bring to an overall memory saving of about 87% with respect to an unoptimized implementation of the tables. Computational performances of the encoder have been improved by increasing the degree of parallelism through the use of priority cascading logic. With the proposed approaches the CAVLC encoder is capable of real time compression of 1080p HDTV video streams, coded in YCbCr 4:2:0, when it is implemented with a low-end Xilinx Spartan 3 FPGA, where the encoder achieves an operation frequency of 63MHz and requires an area occupancy of 2200 LUTs.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
