In this study, a new context-adaptive variable length-coding encoder architecture is proposed particularly aimed to be implemented with field programmable logics (FPL) like FPGAs. The design implements different approaches in order to minimise the area cost as well as to speed up the coding efficiency, which allows real-time compression of 1080 p video streams coded in YCbCr 4:2:0 format. Priority cascading logics have been implemented in order to increase the parallelisation degree of the pre-coding stage, thus favouring the limitation of the number of clock cycles needed for the extraction of symbols from the input data, whereas the employment of the arithmetic table elimination technique has allowed a large-area reduction of the encoder thanks to the elimination of 18 of the 38 tables needed for the encoding stage. The design achieves real time elaboration with an operation frequency of 63 MHz and occupies 2200 look-up table (LUT)s when implemented on a low-cost, low-end XILINX Spartan 3 FPGA, thus overcoming the most recent FPL implementation and making this encoder quite comparable both in terms of area and speed with some recently proposed ASIC implementations, so that it turns out to be a valid alternative also for application specific implementations.
Design of a context-adaptive variable length encoderfor real-time video compression on reconfigurable platforms
LICCIARDO, GIAN DOMENICO;
2012-01-01
Abstract
In this study, a new context-adaptive variable length-coding encoder architecture is proposed particularly aimed to be implemented with field programmable logics (FPL) like FPGAs. The design implements different approaches in order to minimise the area cost as well as to speed up the coding efficiency, which allows real-time compression of 1080 p video streams coded in YCbCr 4:2:0 format. Priority cascading logics have been implemented in order to increase the parallelisation degree of the pre-coding stage, thus favouring the limitation of the number of clock cycles needed for the extraction of symbols from the input data, whereas the employment of the arithmetic table elimination technique has allowed a large-area reduction of the encoder thanks to the elimination of 18 of the 38 tables needed for the encoding stage. The design achieves real time elaboration with an operation frequency of 63 MHz and occupies 2200 look-up table (LUT)s when implemented on a low-cost, low-end XILINX Spartan 3 FPGA, thus overcoming the most recent FPL implementation and making this encoder quite comparable both in terms of area and speed with some recently proposed ASIC implementations, so that it turns out to be a valid alternative also for application specific implementations.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
