In order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided.
CDVS: STM Detector Hw accelerator feasibility study and demonstrator
LICCIARDO, GIAN DOMENICO;VIGLIAR, MARIO;
2013-01-01
Abstract
In order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided.File in questo prodotto:
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