An FPGA optimization of a multiple resolution architecture for LDR to HDR image conversion

An architecture capable of performing the inverse Tone Mapping to convert a Low Dynamic Range image into a High Dynamic Range one is proposed. The proposed image processor is specifically designed for a Field Programmable Gate Array implementation. The design exploits the presence of specific blocks in the Field Programmable Logic board, dedicated to the implementation of memories, in order to develop an efficient implementation to process images having a resolution up to 4K UHDTV. The proposed implementation is developed avoiding frame buffers to obtain a design showing low power and a reduced area, in addition to a real-Time processing of the image up to Full-HD frames. The proposed scheme achieves state-of-The-Art performances and is a lot more flexible than previously developed single resolution architectures.