In this paper an H.264/AVC baseline profile encoder is proposed, designed to be implemented on the STMicroelectronics SPEAr customizable SoC family. Computational intensive modules, like motion estimation and compensation, have been implemented in hardware and prototyped on a Xilinx FPGA where they operate at the maximum frequency of 56.179 MHz. To gain a good adaptiveness for different aims, the variable length coding and the assembly of the output bitstream run on the embedded ARM processor. The high speed obtained and PSNR values of about 35 dB show that the architecture proposed can be successful implemented on low-cost platform also for real time applications.
An H.264 Encoder for Real Time Video Processing Designed for SPEAr Customizable System-on-Chip Family
LICCIARDO, GIAN DOMENICO;
2007
Abstract
In this paper an H.264/AVC baseline profile encoder is proposed, designed to be implemented on the STMicroelectronics SPEAr customizable SoC family. Computational intensive modules, like motion estimation and compensation, have been implemented in hardware and prototyped on a Xilinx FPGA where they operate at the maximum frequency of 56.179 MHz. To gain a good adaptiveness for different aims, the variable length coding and the assembly of the output bitstream run on the embedded ARM processor. The high speed obtained and PSNR values of about 35 dB show that the architecture proposed can be successful implemented on low-cost platform also for real time applications.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
