Abstract High resolution video (720p, 1080i and 1080p frame sizes, up to 60 fps), even if widespread in prosumer/consumer markets, still represents an absolute challenge in the embedded and low power devices, especially due to the increasing complexity of compression schemes. H.264/AVC represents actual de facto standard for both excellent quality and low-bandwidth results. Motion estimation step (ME), for FullHD video, needs up to 80% time of the whole compression demands, if tuned to achieve optimal PSNR ratios. Simplest algorithms, often used to reduce the total computing time, don't meet the requirements in terms of final quality of motion prediction, while “early stopping” schemes suffer of local minima issues when not properly initialized. In this work we present a customizable solution for ME, tailored for SoC/MPSoC inclusion, able to perform different classes of search algorithms, reprogrammable from host CPU even when the coprocessor is encoding. Particular focus has been placed on the processing elements, designed to be easily reconfigured to implement different math and/or logical and/or routing operations. Phase oriented early stopping technique is proposed. Finally, the architecture designed in VHDL has been tested with the UMHEX algorithm for H.264 ME, as proof of concept. FPGA synthesis results are reported.

Algorithm and processor co-design for fast computation in real time HD motion estimation

RAICONI, Giancarlo;
2011

Abstract

Abstract High resolution video (720p, 1080i and 1080p frame sizes, up to 60 fps), even if widespread in prosumer/consumer markets, still represents an absolute challenge in the embedded and low power devices, especially due to the increasing complexity of compression schemes. H.264/AVC represents actual de facto standard for both excellent quality and low-bandwidth results. Motion estimation step (ME), for FullHD video, needs up to 80% time of the whole compression demands, if tuned to achieve optimal PSNR ratios. Simplest algorithms, often used to reduce the total computing time, don't meet the requirements in terms of final quality of motion prediction, while “early stopping” schemes suffer of local minima issues when not properly initialized. In this work we present a customizable solution for ME, tailored for SoC/MPSoC inclusion, able to perform different classes of search algorithms, reprogrammable from host CPU even when the coprocessor is encoding. Particular focus has been placed on the processing elements, designed to be easily reconfigured to implement different math and/or logical and/or routing operations. Phase oriented early stopping technique is proposed. Finally, the architecture designed in VHDL has been tested with the UMHEX algorithm for H.264 ME, as proof of concept. FPGA synthesis results are reported.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11386/3048516
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