Double conductance minima in graphene field-effect transistors

In this study we present measurements on Cr/Au contacted long-channel (10 µm) graphene transistors on Si-SiO2 substrate and we report the observation of hysteresis as well as double dips in the transfer characteristics. Charge trapped in the surrounding dielectric and in particular in silanol groups at the SiO2 surface is at the origin of the hysteresis; while, the gradient of carriers along the channel caused by electron transfer from the graphene to the Au/Cr contacts and the band shift induced by the backgate voltage and the SiO2-trapped charge are proposed to account for the double dip feature. We show in particular that p–n junctions are spontaneously formed by charge transfer between the graphene and the electrodes and that a double Dirac point can be achieved when low-resistivity contacts are fabricated. We further clarify the role of charge stored at the SiO2 interface in the formation of the double dip and we propose partial charge pinning at the contacts to explain the current saturation observed at high back-gate voltages. Accordingly, a phenomenological modeling of experimental data is successfully implemented. We finally show that the hysteresis, enhanced by a double dip, can conveniently be exploited to build graphene-based memory devices.