Gabor filters gained a great importance in multimedia processing and visual search applications, thanks to the good spatial frequency and position selectivity, despite of their heavy computational complexity. Further, the large number of parameters to be imposed sets a number of trade-offs between accuracy and complexity making the use of Gabor filters very challenging. In this work, a number of criteria are exploited for a careful choice of the parameters, in order to allow implementing accurate two-dimensional filters, with a computational complexity that can be adapted to target platforms with different capabilities. In order to show this, three hardware designs of a Gabor filter-based edge detection system are derived, implementing two and four orientations, all capable of real-time processing with different Area-Delay-Power performances and accuracies. The derived designs have been implemented on a FPGA-based ASIC prototyping system and synthesized in 90nm CMOS std-cells, returning a maximum operating frequency of 179 MHz and 350 MHz, respectively. Therefore, the proposed filters achieve state-of-the-art performances with the best throughput of 86 and 168 Full-HD (1920×1080 pixels) frames-per-second, for FPGA and std-cell implementations, respectively.
Design Criteria for Real-time Processing of HW Gabor Filters in Visual Search
LICCIARDO, Gian Domenico
;CAPPETTA, CARMINE;DI BENEDETTO, Luigi
2018-01-01
Abstract
Gabor filters gained a great importance in multimedia processing and visual search applications, thanks to the good spatial frequency and position selectivity, despite of their heavy computational complexity. Further, the large number of parameters to be imposed sets a number of trade-offs between accuracy and complexity making the use of Gabor filters very challenging. In this work, a number of criteria are exploited for a careful choice of the parameters, in order to allow implementing accurate two-dimensional filters, with a computational complexity that can be adapted to target platforms with different capabilities. In order to show this, three hardware designs of a Gabor filter-based edge detection system are derived, implementing two and four orientations, all capable of real-time processing with different Area-Delay-Power performances and accuracies. The derived designs have been implemented on a FPGA-based ASIC prototyping system and synthesized in 90nm CMOS std-cells, returning a maximum operating frequency of 179 MHz and 350 MHz, respectively. Therefore, the proposed filters achieve state-of-the-art performances with the best throughput of 86 and 168 Full-HD (1920×1080 pixels) frames-per-second, for FPGA and std-cell implementations, respectively.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.