A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.
A Fast and Area Efficient Complementary pass-transistor logic carry-skip adder
NAPOLI, ETTORE
1997-01-01
Abstract
A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.File in questo prodotto:
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