The behaviour of a deep depletion SOI LDMOS is thoroughly analyzed in this paper. Deep depletion of the substrate for a SOI device has been recently proposed as an innovative technique to design power devices featuring a transient breakdown higher than the static breakdown. The deep depletion is a dynamic effect that allows the design of a whole new generation of SOI power devices providing improved performances. Eligible applications are power conditioning circuits in which the device sustains transient voltages higher than bus voltage such as the flyback converter and the resonant circuits. In this paper numerical simulations are used to analyze the behaviour of the device together with the effect of temperature and substrate carrier generation time on the duration of the transient breakdown phase. Numerical results show that the newly proposed "deep depletion SOI device", a SOI power LDMOS using P substrate, exhibit 190V static breakdown voltage while sustains transient overvoltages up to 290V. Furthermore, mixed-mode simulation of a complete Class E resonant converter using the proposed deep depletion SOI device is presented.
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