In the paper new implementations of double edge-triggered (DET) flip-flops using one latch are presented. In the proposed circuits data are sampled into the latch during a short transparency period for each edge of the clock signal. Three implementations (dynamic, semi-static and static) of the one-latch DET flip-flop are presented and compared with standard two-latch DETs. SPICE simulations of power dissipation as a function of the switching activity of input signal are presented. One-latch DETs have reduced transistor count and lower power dissipation with respect to previously reported DET flip-flops. Power saving is relevant when an array of flip-flops share a single clock driver and for large input signal transition probability

Power Dissipation in One-latch and Two-latch Double Edge Triggered Flip-Flops

NAPOLI, ETTORE
1999-01-01

Abstract

In the paper new implementations of double edge-triggered (DET) flip-flops using one latch are presented. In the proposed circuits data are sampled into the latch during a short transparency period for each edge of the clock signal. Three implementations (dynamic, semi-static and static) of the one-latch DET flip-flop are presented and compared with standard two-latch DETs. SPICE simulations of power dissipation as a function of the switching activity of input signal are presented. One-latch DETs have reduced transistor count and lower power dissipation with respect to previously reported DET flip-flops. Power saving is relevant when an array of flip-flops share a single clock driver and for large input signal transition probability
1999
0-7803-5682-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4772684
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