A novel architecture for real time Synthetic Aperture Radar (SAR) signal processing is presented. Presently, notwithstanding the use of expensive parallel computers and FET techniques, available SAR processors are unable to achieve real time performance. The proposed architecture achieves real time processing by using a recently proposed signum coded algorithm and time domain processing implemented in a custom VLSI architecture based on systolic arrays
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing
NAPOLI, ETTORE;
1999-01-01
Abstract
A novel architecture for real time Synthetic Aperture Radar (SAR) signal processing is presented. Presently, notwithstanding the use of expensive parallel computers and FET techniques, available SAR processors are unable to achieve real time performance. The proposed architecture achieves real time processing by using a recently proposed signum coded algorithm and time domain processing implemented in a custom VLSI architecture based on systolic arraysFile in questo prodotto:
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