The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C 2MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25μm technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.
A high-speed sense-amplifier based flip-flop
NAPOLI, ETTORE;
2005-01-01
Abstract
The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C 2MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25μm technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.File in questo prodotto:
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