Over the last years, timing channels that exploit resources shared at the microarchitectural level have attracted a lot of attention. The majority of such side-channel attacks target CPU caches. Cache-based side-channel attacks are based on monitoring cache accesses performed by a victim process through measurements of access times by a spy process that shares the cache with the victim. Among the countermeasures proposed to frustrate cache-based side-channel attacks, cache partitioning seems most effective. The recently introduced Cache Allocation Technology (CAT) enables fine control over the LLC and how cores allocate into it. In this work, we introduce the problem of optimizing cache partitioning under dynamically configurable schemes such as Intel CAT, in the perspective of thwarting access-based side-channel attacks.

Optimal partitioning of LLC in CAT-enabled CPUs to prevent side-channel attacks

Fiore, Ugo;
2018

Abstract

Over the last years, timing channels that exploit resources shared at the microarchitectural level have attracted a lot of attention. The majority of such side-channel attacks target CPU caches. Cache-based side-channel attacks are based on monitoring cache accesses performed by a victim process through measurements of access times by a spy process that shares the cache with the victim. Among the countermeasures proposed to frustrate cache-based side-channel attacks, cache partitioning seems most effective. The recently introduced Cache Allocation Technology (CAT) enables fine control over the LLC and how cores allocate into it. In this work, we introduce the problem of optimizing cache partitioning under dynamically configurable schemes such as Intel CAT, in the perspective of thwarting access-based side-channel attacks.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11386/4780463
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