A new hardware design of digital system focused to Space Vector Pulse Width Modulation technique is shown. The system performs the real-time control of the output voltage amplitude and of the switching frequency as well as the delay between the three phase output voltages in order to change the direction of rotation of an asynchronous motor. Although the design can be applied to digital control devices, we focused to Field Programmable Gate Array and both architecture and experimental results are shown. The idea is to pre-calculate the dwell-times, which are normalized to the maximum amplitude modulation index, and to relate them at the corresponding switching configurations of the inverter. They are stored in the internal Look-Up Tables and all the operations are performed without any external devices or any external reference signals. A three-phase power inverter prototype supplies a 380VAC − 50Hz − 750W asynchronous motor with on-board Altera Cyclone V FPGA. Our architecture demands 243 FFs and 324 LUTs, which are the 0.66% and 1.75% of the overall system, respectively, avoids internal DSPs and has a low dynamic power dissipation of 0.54mW at a system clock frequency of 100MHz. Our proposal interests those applications where the FPGA manages the overall power system and limited resources are required.

Design of digital controller for SVPWM algorithm with real-time control of the output amplitude and switching frequency

Donisi A.;Di Benedetto L.;Licciardo G. D.;Rubino A.;
2021

Abstract

A new hardware design of digital system focused to Space Vector Pulse Width Modulation technique is shown. The system performs the real-time control of the output voltage amplitude and of the switching frequency as well as the delay between the three phase output voltages in order to change the direction of rotation of an asynchronous motor. Although the design can be applied to digital control devices, we focused to Field Programmable Gate Array and both architecture and experimental results are shown. The idea is to pre-calculate the dwell-times, which are normalized to the maximum amplitude modulation index, and to relate them at the corresponding switching configurations of the inverter. They are stored in the internal Look-Up Tables and all the operations are performed without any external devices or any external reference signals. A three-phase power inverter prototype supplies a 380VAC − 50Hz − 750W asynchronous motor with on-board Altera Cyclone V FPGA. Our architecture demands 243 FFs and 324 LUTs, which are the 0.66% and 1.75% of the overall system, respectively, avoids internal DSPs and has a low dynamic power dissipation of 0.54mW at a system clock frequency of 100MHz. Our proposal interests those applications where the FPGA manages the overall power system and limited resources are required.
978-1-7281-9201-7
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4806723
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 0
social impact