VIGLIAR, MARIO
VIGLIAR, MARIO
Dipartimento di Informatica/DI
CDVS: STM Detector Hw accelerator feasibility study and demonstrator
2013-01-01 Thomas, Boesch; Giuseppe, Desoli; Licciardo, GIAN DOMENICO; Vigliar, Mario; Claudio, Parrella; Arcangelo, Bruna
Hardware coprocessor for stripe-based interest point detection
2013-01-01 Vigliar, Mario; Licciardo, GIAN DOMENICO
Memory analysis of Interest Point Detector and Compact Descriptor algorithms
2012-01-01 Arcangelo, Bruna; Danilo, Pau; Claudio, Parrella; Gianfranco Di Nuzzo, ; Vigliar, Mario; Licciardo, GIAN DOMENICO; Napoli, Ettore; Giorgio, Lopez
Real-Time Low-Power FPGA Architecture for Stereo Vision
2017-01-01 Puglia, Luca; Vigliar, Mario; Raiconi, Giancarlo
SASC: A hardware string alignment coprocessor for stereo correspondence2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
2012-01-01 Vigliar, Mario; Fratello, Michele; Puglia, Luca; Raiconi, Giancarlo
SASCr2: Enhanced hardware string alignment coprocessor for stereo correspondence
2014-01-01 Vigliar, Mario; Puglia, Luca; Fratello, Michele; Raiconi, Giancarlo
SASCr3: A Real Time Hardware Coprocessor for Stereo Correspondence
2014-01-01 Puglia, Luca; Vigliar, Mario; Raiconi, Giancarlo
Toward hardware implementation of DoG
2012-01-01 Danilo, Pau; Vigliar, Mario; Licciardo, GIAN DOMENICO; Emanuele, Plebani; Arcangelo, Bruna; Claudio, Parrella
Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit
2017-01-01 Licciardo, GIAN DOMENICO; Cappetta, Carmine; DI BENEDETTO, Luigi; Vigliar, Mario
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| CDVS: STM Detector Hw accelerator feasibility study and demonstrator | 1-gen-2013 | Thomas, Boesch; Giuseppe, Desoli; Licciardo, GIAN DOMENICO; Vigliar, Mario; Claudio, Parrella; Arcangelo, Bruna | |
| Hardware coprocessor for stripe-based interest point detection | 1-gen-2013 | Vigliar, Mario; Licciardo, GIAN DOMENICO | |
| Memory analysis of Interest Point Detector and Compact Descriptor algorithms | 1-gen-2012 | Arcangelo, Bruna; Danilo, Pau; Claudio, Parrella; Gianfranco Di Nuzzo, ; Vigliar, Mario; Licciardo, GIAN DOMENICO; Napoli, Ettore; Giorgio, Lopez | |
| Real-Time Low-Power FPGA Architecture for Stereo Vision | 1-gen-2017 | Puglia, Luca; Vigliar, Mario; Raiconi, Giancarlo | |
| SASC: A hardware string alignment coprocessor for stereo correspondence2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) | 1-gen-2012 | Vigliar, Mario; Fratello, Michele; Puglia, Luca; Raiconi, Giancarlo | |
| SASCr2: Enhanced hardware string alignment coprocessor for stereo correspondence | 1-gen-2014 | Vigliar, Mario; Puglia, Luca; Fratello, Michele; Raiconi, Giancarlo | |
| SASCr3: A Real Time Hardware Coprocessor for Stereo Correspondence | 1-gen-2014 | Puglia, Luca; Vigliar, Mario; Raiconi, Giancarlo | |
| Toward hardware implementation of DoG | 1-gen-2012 | Danilo, Pau; Vigliar, Mario; Licciardo, GIAN DOMENICO; Emanuele, Plebani; Arcangelo, Bruna; Claudio, Parrella | |
| Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit | 1-gen-2017 | Licciardo, GIAN DOMENICO; Cappetta, Carmine; DI BENEDETTO, Luigi; Vigliar, Mario |