In order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided.
Titolo: | CDVS: STM Detector Hw accelerator feasibility study and demonstrator |
Autori: | |
Data di pubblicazione: | 2013 |
Abstract: | In order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided. |
Handle: | http://hdl.handle.net/11386/4481259 |
Appare nelle tipologie: | 4.1 Contributi in Atti di convegno |
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