A new radix-3 partitioning method of natural numbers, derived by the weight partition theory, is employed to build a multiplier-less circuit well-suited for multimedia filtering applications. The partitioning method allows to conveniently pre- multiply 32 bit floating-point (FP32) filter coefficients with the smallest set of parts composing an unsigned integer input. In this way, similarly to the Distributed Arithmetic, shifters and recoding circuitry, typical of other well-known multiplier circuits, are completely substituted with simplified floating-point adders. Compared to the existent literature, targeted to both FPGA and std_cell technology, the proposed solution achieves state-of-the-art performances in terms of elaboration velocity, achieving a critical path delay of about 2 ns both on a Xilinx Virtex 7 and with CMOS 90nm std_cells.
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