In this paper an architecture design of a hardware accelerator capable to expand the dynamic range of LDR (Low-Dynamic Range) images to the 32bits-HDR (High-Dynamic Range) counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, in order to elaborate a Full-HD (1920x1080 pixels) image in 16.6ms (60fps) on Field-Programmable Logic (FPL), by processing the incoming pixels in streaming order, without frame buffers. In this way, the design avoids the use of external DRAM and can be tightly coupled with acquiring devices, thus to enable the implementation of smart sensors. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different target platforms from FPLs to ASICs, obtaining, in both implementations, state-of-the-art performances.
Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images
LICCIARDO, GIAN DOMENICO;D'ARIENZO, ANTONIO;RUBINO, Alfredo
2015
Abstract
In this paper an architecture design of a hardware accelerator capable to expand the dynamic range of LDR (Low-Dynamic Range) images to the 32bits-HDR (High-Dynamic Range) counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, in order to elaborate a Full-HD (1920x1080 pixels) image in 16.6ms (60fps) on Field-Programmable Logic (FPL), by processing the incoming pixels in streaming order, without frame buffers. In this way, the design avoids the use of external DRAM and can be tightly coupled with acquiring devices, thus to enable the implementation of smart sensors. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different target platforms from FPLs to ASICs, obtaining, in both implementations, state-of-the-art performances.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
