The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature.
|Titolo:||Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories|
|Data di pubblicazione:||2016|
|Appare nelle tipologie:||1.1.1 Articolo su rivista con DOI|