Analytical description of the input capacitance of 4H-SiC DMOSFET’s in presence of oxide-semiconductor interface traps

An analytical model of the input capacitance of Vertical DMOSFETs in 4H-SiC is presented, in order to provide an accurate instrument for the quantitative analysis and synthesis of the device and for accurate interpretations of C-V measurements. The model describes the charge dynamics into the channel and the accumulation region of the device, in presence of the energy dependent oxide-semiconductor interface trapped charge. Comparisons with numerical simulations show that the model correctly describes the variations of the surface potential induced by the gate voltage in all the device regions covered by the oxide, from accumulation to strong inversion of the channel, and to correctly relate them to the capacitance variations.