In this paper, an analytical model is presented to describe the input capacitance of Power-MOSFETs in 4H polytype of Silicon Carbide (4H-SiC). In order to provide an instrument for accurate interpretations of C-V measurements and for a deeper understanding of the device operations, the model describes the charge variations induced by the presence of the oxide-semiconductor interface trapped charge. Their energy dependence has been accounted to describe the charge dynamics into the channel and the accumulation layer and proved by comparisons with numerical simulations.

SiO2/4H-SiC interface traps effects on the input capacitance of DMOSFET

LICCIARDO, GIAN DOMENICO;DI BENEDETTO, LUIGI
2016

Abstract

In this paper, an analytical model is presented to describe the input capacitance of Power-MOSFETs in 4H polytype of Silicon Carbide (4H-SiC). In order to provide an instrument for accurate interpretations of C-V measurements and for a deeper understanding of the device operations, the model describes the charge variations induced by the presence of the oxide-semiconductor interface trapped charge. Their energy dependence has been accounted to describe the charge dynamics into the channel and the accumulation layer and proved by comparisons with numerical simulations.
9781509030835
9781509030835
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11386/4679463
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