A new analytical model of the 4H-SiC DMOSFET is proposed that is capable to predict the forward operation of the device in a wide range of temperature, by including in its DC current-voltage characteristics the effects of the parasitic resistances, of the insulator-semiconductor interface traps on the threshold voltage and channel mobility, as well as their temperature dependences. The accuracy of the model has been verified by comparisons with numerical simulations using interface trap density varying in the range [0; 1014]cm-2 eV-1 and a temperature operation up to 500K. Comparisons with experimental data taken on 1.2kV commercial devices validate the model.
|Titolo:||Modelling the I-V-T characteristics of 4H-SiC DMOSFET in presence of SiO2/SiC interface traps and fixed oxide|
|Data di pubblicazione:||2016|
|Appare nelle tipologie:||4.1.1 Proceedings con DOI|