We characterized a hybrid device consisting of a graphene/silicon (Gr/Si) Schottky diode in parallel with a Gr/SiO2/Si capacitor for high-performance photodetection. The device, fabricated by transfer of commercial graphene on low-doped n-type Si substrate, achieves photoresponse as high as 3A/W and normalized detectivity higher than 3.5x1012cmHz1/2/W in the visible range. The device exhibits a photocurrent exceeding the forward current, as photo-generated minority carriers, accumulated at Si/SiO2 interface of the Gr/SiO2/Si capacitor, diffuse to the Gr/Si junction. We show that the same mechanism, when due to thermally generated carriers, although usually neglected or disregarded, causes the increased leakage often measured in Gr/Si heterojunctions. At room temperature, we measure a zero-bias Schottky barrier height of 0.52 eV, as well as an effective Richardson constant A**=4x10-5Acm-2K-2 and an ideality factor n≈3.6, explained by a thin (< 1nm) oxide layer at the Gr/Si interface.

Hybrid Graphene/Silicon Schottky photodiode with intrinsic gating effect

LUONGO, GIUSEPPE;DI BARTOLOMEO, Antonio
2017-01-01

Abstract

We characterized a hybrid device consisting of a graphene/silicon (Gr/Si) Schottky diode in parallel with a Gr/SiO2/Si capacitor for high-performance photodetection. The device, fabricated by transfer of commercial graphene on low-doped n-type Si substrate, achieves photoresponse as high as 3A/W and normalized detectivity higher than 3.5x1012cmHz1/2/W in the visible range. The device exhibits a photocurrent exceeding the forward current, as photo-generated minority carriers, accumulated at Si/SiO2 interface of the Gr/SiO2/Si capacitor, diffuse to the Gr/Si junction. We show that the same mechanism, when due to thermally generated carriers, although usually neglected or disregarded, causes the increased leakage often measured in Gr/Si heterojunctions. At room temperature, we measure a zero-bias Schottky barrier height of 0.52 eV, as well as an effective Richardson constant A**=4x10-5Acm-2K-2 and an ideality factor n≈3.6, explained by a thin (< 1nm) oxide layer at the Gr/Si interface.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4686834
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