A Bit-Line Voltage Sensing Circuit With Fused Offset Compensation and Cancellation Scheme

A systematic offset voltage occurs in sense amplifiers for SRAMs, mainly due to the mismatch between the threshold voltages of MOS transistors. This offset affects the reading operations of SRAMs in terms of accuracy, delay and power consumption. In this paper, a bit-line voltage sense amplifier is presented, which combines offset compensation and cancellation features. The circuit operations are carried out in four phases, in which two CMOS amplifiers are used as line buffers and they are pre-charged in the high voltage gain region in order to reduce the effects of the offset. The proposed sense amplifier has been designed and prototyped in 180 nm CMOS technology. It is capable to correct a voltage offset up to 100 mV and exhibits a minimum access time of 58 ps. These results overcome other solutions in applications where sub-threshold operations are not required and an aggressive voltage scaling is not convenient.