A Fully FPGA Implementation of SVPWM for Three-phase Inverters without External Reference Signals

In this paper we propose a novel method to implement Space Vector Pulse Width Modulation algorithm in Field Programmable Gate Array hardware. It is based on storing pre-calculated and normalized dwell times in internal Look-Up Tables of FPGA and on the evaluation through FPGA of the effective dwell times, as function of the modulation index, and of the relative configurations of the power transistors. The input data is the modulation index, instead the switching frequency and the output frequency are defined when the normalized dwell times are calculated. This method permits to significantly reduce hardware resources and computational cost of the FPGA. Although it is proposed to drive three-phase motor in open-loop control, the modulation index can be linearly changed from the user in real-time so that a start-up ramp of the output voltage amplitude ca be performed, for example. The method is implemented on FPGA Artix7 from Xilinx, Inc. by using 420 LUT and 245 FF, which are, respectively, 2.2% and 0.59% of the overall resources, without requiring any Digital Signal Processing and BRAMs. Experimental results show the gate control signals of the power transistors to generate an output voltage at 50Hz with a start-up voltage ramp and a switching frequency of 9.75kHz.