Design of Fixed-Width Multipliers with Linear Compensation Function

This paper focuses on fixed-width multipliers with linear compensation function by investigating in detail the effect of coefficients quantization. New fixed-width multiplier topologies, with different accuracy versus hardware complexity trade-off, are obtained by varying the quantization scheme. Two topologies are in particular selected as the most effective ones. The first one is based on a uniform coefficient quantization, while the second topology uses a nonuniform quantization scheme. The novel fixed-width multiplier topologies exhibit better accuracy with respect to previous solutions, close to the theoretical lower bound. The electrical performances of the proposed fixed-width multipliers are compared with previous architectures. It is found that in most of the investigated cases the new topologies are Pareto-optimal regarding the area-accuracy trade-off. We also present experimental results, obtained from a simple multiply-accumulate unit implemented in a 90 nm CMOS technology.