Background identification is a common feature in many video processing systems. The paper proposes two hardware implementations of the OpenCV version of the Gaussian Mixture Model (GMM), a background identification algorithm. The implemented version of the algorithm allows a fast initialization of the background model while an innovative, hardware oriented, formulation of the GMM equations makes the proposed circuits able to perform real time background identification on High Definition (HD) video sequences with frame size 19201080. The first of the two circuits has been designed having commercial FPGA devices as target. When implemented on Virtex6 vlx75t, the proposed circuit processes 91 HD fps and uses 3% of FPGA logic resources. The second circuit has been oriented to the implementation in UMC-90nm CMOS standard cell technology and is proposed in two versions. Both versions can process at a frame rate higher than 60 HD fps. The first version uses the constant voltage scaling technique to provide a low power implementation. It provides silicon area occupation of 28847 m2 and energy dissipation per pixel of 15.3 pJ/pixel. The second version is designed to reduce silicon area utilization and occupies 21847 m2 with an energy dissipation of 49.4 pJ/pixel.

ASIC and FPGA implementation of the Gaussian Mixture Model algorithm for real-time segmentation of High Definition video

NAPOLI, ETTORE
2013-01-01

Abstract

Background identification is a common feature in many video processing systems. The paper proposes two hardware implementations of the OpenCV version of the Gaussian Mixture Model (GMM), a background identification algorithm. The implemented version of the algorithm allows a fast initialization of the background model while an innovative, hardware oriented, formulation of the GMM equations makes the proposed circuits able to perform real time background identification on High Definition (HD) video sequences with frame size 19201080. The first of the two circuits has been designed having commercial FPGA devices as target. When implemented on Virtex6 vlx75t, the proposed circuit processes 91 HD fps and uses 3% of FPGA logic resources. The second circuit has been oriented to the implementation in UMC-90nm CMOS standard cell technology and is proposed in two versions. Both versions can process at a frame rate higher than 60 HD fps. The first version uses the constant voltage scaling technique to provide a low power implementation. It provides silicon area occupation of 28847 m2 and energy dissipation per pixel of 15.3 pJ/pixel. The second version is designed to reduce silicon area utilization and occupies 21847 m2 with an energy dissipation of 49.4 pJ/pixel.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4772688
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