A Hardware Architecture for SVPWM Digital Control with Variable Carrier Frequency and Amplitude

A novel digital circuit for the Space Vector Pulse Width Modulation algorithm used in three-phase power inverters is shown. From an analysis of the vector representation of the three-phase triad, the dwell-times evaluation is optimized reducing the needed resource of the hardware. Our proposal is based on the use of only one-sixth of the vectorial plane and on a pre-calculation of the dwell-times in terms of the maximum modulation index and the minimum carrier frequency. Once obtained the normalized dwell-times, an optimized hardware architecture is proposed to evaluate the effective dwell-times by changing in real-time the wanted values of the carrier frequency and of the amplitude. Our architecture excludes the use of external reference signals or processors. We experimentally implement it both on a low cost FPGA Artix-VII and on a more performing Cyclone-V. Finally, classical and advanced SVPWM techniques are proposed to show the flexibility of our architecture.