This paper presents an automatic design space exploration using processor design knowledge for the multi-objective optimisation of a superscalar microarchitecture enhanced with selective load value prediction (SLVP). We introduced new important SLVP parameters and determined their influence regarding performance, energy consumption, and thermal dissipation. We significantly enlarged initial processor design knowledge expressed through fuzzy rules and we analysed its role in the process of automatic design space exploration. The proposed fuzzy rules improve the diversity and quality of solutions, and the convergence speed of the design space exploration process. Experiments show that a set-associative prediction table is more effective than a direct mapped table and that 86% of the configurations in the Pareto front use multiple values per load. In conclusion, our experiments show that integrating an SLVP module into a superscalar microarchitecture is hardware feasible; in comparison with the case without SLVP, performance is better, energy consumption is lower, and the temperatures inside the chip decreases, remaining below 75°C.

Performance and Energy Optimisation in CPUs through Fuzzy Knowledge Representation

Fiore, Ugo;
2019

Abstract

This paper presents an automatic design space exploration using processor design knowledge for the multi-objective optimisation of a superscalar microarchitecture enhanced with selective load value prediction (SLVP). We introduced new important SLVP parameters and determined their influence regarding performance, energy consumption, and thermal dissipation. We significantly enlarged initial processor design knowledge expressed through fuzzy rules and we analysed its role in the process of automatic design space exploration. The proposed fuzzy rules improve the diversity and quality of solutions, and the convergence speed of the design space exploration process. Experiments show that a set-associative prediction table is more effective than a direct mapped table and that 86% of the configurations in the Pareto front use multiple values per load. In conclusion, our experiments show that integrating an SLVP module into a superscalar microarchitecture is hardware feasible; in comparison with the case without SLVP, performance is better, energy consumption is lower, and the temperatures inside the chip decreases, remaining below 75°C.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11386/4780501
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