This work proposes a new ultra low-power fault detection system, suitable for extreme edge or in-sensor computing. The system is composed of a hybrid HW/SW architecture: a hardware auto-encoder (AE) is always on at the edge for anomaly detection (AD), and of a software convolutional neural network (CNN) is activated only if the anomaly is detected for its classification. To achieve low area and energy requirements, the AE exploits an original partially binarization scheme, while the CNN shares the feature extraction module with the AE. The implementation of the AE on a Xilinx Artix-7 FPGA demonstrates that it is capable to manage in real-time sensors with a maximum Output Data Rate (ODR) of 365 kHz with a power dissipation of 122 mW. Best synthesis results with TSMC CMOS 65 nm standard cells show a power consumption of 138mu{W}{MHz} and an area occupation of 0.49 mm2 when real-time operations are set, enabling the possibility to integrate the complete HW accelerator in the auxiliary circuitry that typically equips inertial MEMS and on the same die. Comparisons with the current literature show that the proposed system obtains state-of-the-art performances in terms of accuracy and compactness.

Low-Power Anomaly Detection and Classification System based on a Partially Binarized Autoencoder for In-Sensor Computing

Vitolo P.;Licciardo G. D.;Di Benedetto L.;Liguori R.;Rubino A.;
2021

Abstract

This work proposes a new ultra low-power fault detection system, suitable for extreme edge or in-sensor computing. The system is composed of a hybrid HW/SW architecture: a hardware auto-encoder (AE) is always on at the edge for anomaly detection (AD), and of a software convolutional neural network (CNN) is activated only if the anomaly is detected for its classification. To achieve low area and energy requirements, the AE exploits an original partially binarization scheme, while the CNN shares the feature extraction module with the AE. The implementation of the AE on a Xilinx Artix-7 FPGA demonstrates that it is capable to manage in real-time sensors with a maximum Output Data Rate (ODR) of 365 kHz with a power dissipation of 122 mW. Best synthesis results with TSMC CMOS 65 nm standard cells show a power consumption of 138mu{W}{MHz} and an area occupation of 0.49 mm2 when real-time operations are set, enabling the possibility to integrate the complete HW accelerator in the auxiliary circuitry that typically equips inertial MEMS and on the same die. Comparisons with the current literature show that the proposed system obtains state-of-the-art performances in terms of accuracy and compactness.
978-1-7281-8281-0
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4806721
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