The parer illustrates a new FPGA hardware architecture for the Space Vector Pulse Width Modulation, which decompose the dwell-times expressions using the Taylor Series. The difference from the state of the arts is the disuse of other resources, like external reference signals or Digital Signal Processor, as well as specific architectures, like CORDIC core or Look Up Table-based approaches. All the calculations are done by a 32 bit fixed-point Arithmetic Logic Unit, which can perform a real time variation of the output amplitude. The architecture has been implemented on a Xilinx Artix VII FPGA XC7A35T1CPG236C requiring 1967 LUTs and 492 Flip Flops, respectively, the 9.46 % and 1.18 % of the overall resources, and a dynamic power consumption of 1 mW.
FPGA HardWare Architecture for SVPWM Based on a Taylor Series Decomposition
Donisi A.;Di Benedetto L.
;Liguori R.;Licciardo G. D.;Rubino A.
2023-01-01
Abstract
The parer illustrates a new FPGA hardware architecture for the Space Vector Pulse Width Modulation, which decompose the dwell-times expressions using the Taylor Series. The difference from the state of the arts is the disuse of other resources, like external reference signals or Digital Signal Processor, as well as specific architectures, like CORDIC core or Look Up Table-based approaches. All the calculations are done by a 32 bit fixed-point Arithmetic Logic Unit, which can perform a real time variation of the output amplitude. The architecture has been implemented on a Xilinx Artix VII FPGA XC7A35T1CPG236C requiring 1967 LUTs and 492 Flip Flops, respectively, the 9.46 % and 1.18 % of the overall resources, and a dynamic power consumption of 1 mW.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
