Role of interface and bulk traps on the capacitance–voltage characteristics of WS2/Al2O3/Si capacitors

This paper reports the capacitance–voltage (CV) characteristics of 2D material based vertical semiconductor oxide semiconductor (SOS) capacitors (CAPs) at different ac frequencies. The SOS structure is made of mechanically exfoliated WS2 flakes, deposited on a p-type silicon substrate covered by Al2O3 dielectric layer. The device exhibits n-type behavior as WS2 goes into accumulation at positive biases on the p-Si, with a nonintentional doping concentration of around 10^17 cm^-3. By double sweeping the DC bias, a hysteresis cycle occurs in the CV response. On the other hand, a low frequency dispersion is observed in the depletion mode implying a low WS2/Al2O3 interface trap density. Our quantitative analysis confirms a low interface trap density of Dit ∼ 10^11 cm^- 2 eV^-1. We also report our observation on a distortion in the CV characteristics, observed as the depletion width expands into the WS2 at negative voltage bias. This feature does not depend on the ac signal frequency. Based on our CV analysis, we have proposed a hypothesis with a schematic band-energy model where the CV distortion is attributed to localized bulk traps in the WS2 located within the first few nm from the WS2/Al2O3 interface.