Approximate computing is a new approach that can help to reduce power consumption in error-resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper, we introduce an adjustable floating-point multiplier in which groups of partial products can be dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjusted at run-time based on the users' requirements. The developed circuits are synthesized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art shows a good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios.
File in questo prodotto:
Non ci sono file associati a questo prodotto.