A Novel Approximate Multiplier Based on Improved Logarithmic and Antilogarithmic Conversions

In this paper, we propose a novel approximate multiplier with error-improved logarithmic and antilogarithmic conversion. In logarithmic multiplication, the forward and backward conversions to the logarithm domain introduce errors in the product. To recover accuracy, we apply an offset when logarithm and antilogarithm are computed, and find suitable values for these offsets in order to make the approximation error with zero mean. The hardware structure of the proposed multiplier is described for signed arithmetic, and a novel hardware-efficient approach, able to compute the sign of the output, is also proposed. Error metrics and synthesis analyses in a 28nm CMOS technology show that our multiplier offers the best accuracy-hardware performance for MRED<4×10-2. Furthermore, remarkable results are achieved also in JPEG compression, exhibiting SSIM and PSNR metrics competitive with the state-of-the-art.