Analytical Error Evaluation and Hardware Implementation of Approximate Negation Circuits

Inexact arithmetic units trade precision for improvements in energy efficiency, silicon area, and speed. Most existing designs focus on non-negative numbers and, when used in real applications, rely on Sign and Magnitude (SM) transformations to deal with signed values mitigating most of the advantages obtained in the first place. This work investigates circuits for the approximate negation of numbers in two’s complement (2’sC) format that offer a middle ground in terms of error and energy efficiency when compared to the exact 2’sC negation and the more aggressive one’s complement (1’sC) negation method, thus obtaining a general purpose tool for approximate computing that can be seamlessly integrated into existing designs. The paper demonstrates that by using this tool it is possible to exploit unsigned approximate arithmetic circuits in signed applications, achieving slightly lower error with no additional power compared to the commonly used 1’sC approximation, or significantly reduced error, while still lowering power dissipation relative to exact 2’sC negation. We derive analytical expressions for error characteristics and present a hardware implementation. The resulting versatile technique can be exploited to compute absolute values or to convert SM representations into 2’sC format. We incorporate the investigated circuits into several approximate architectures using a 14 nm FinFET standard cell library. The resulting designs, when compared with 1’sC negation, are able to improve accuracy (achieving up to 30% error reduction in approximate multipliers and 10dB PSNR gain in H.264 video compression) while still reducing the power dissipation.