Matrix multiplication circuits are widely used as accelerators in 3D graphics, communications, artificial intelligence, and other domains. Recent years have seen significant advances in efficient algorithms for small-dimension matrix multiplication. The AlphaEvolve algorithm for complex-valued matrices achieves rank-48 using only 48 binary multiplications, improving on the naive algorithm (64 multiplications) and the previous best known methods (49 multiplications). Following this development, a new algorithm for real-valued 4×4 matrix multiplication was proposed in June 2025. This work provides an implementation of the algorithm optimized for a VLSI accelerator with parallel access to the input data. Both a one cycle version and two pipelined versions of the circuit are proposed. The results are benchmarked against the naive algorithm commonly employed in commercial accelerators, and an implementation of the Strassen algorithm. Synthesized in a 28 nm CMOS standard cell library, the proposed circuit requires fewer hardware resources than the naive implementation for input bit-widths above approximately 40 bits but the naive implementation achieves higher speed and lower power.
AlphaEvolve-Based Rank-48 Algorithm for 4×4 Real-Valued Matrix Multiplication: 28 nm Implementation and Comparison with Strassen
Ettore Napoli
2026
Abstract
Matrix multiplication circuits are widely used as accelerators in 3D graphics, communications, artificial intelligence, and other domains. Recent years have seen significant advances in efficient algorithms for small-dimension matrix multiplication. The AlphaEvolve algorithm for complex-valued matrices achieves rank-48 using only 48 binary multiplications, improving on the naive algorithm (64 multiplications) and the previous best known methods (49 multiplications). Following this development, a new algorithm for real-valued 4×4 matrix multiplication was proposed in June 2025. This work provides an implementation of the algorithm optimized for a VLSI accelerator with parallel access to the input data. Both a one cycle version and two pipelined versions of the circuit are proposed. The results are benchmarked against the naive algorithm commonly employed in commercial accelerators, and an implementation of the Strassen algorithm. Synthesized in a 28 nm CMOS standard cell library, the proposed circuit requires fewer hardware resources than the naive implementation for input bit-widths above approximately 40 bits but the naive implementation achieves higher speed and lower power.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
