Time-based 8TD SRAM CIM Macro with Low PVT Sensitivity for Edge Devices

Computing-in-Memory (CIM) promises to overcome the von Neumann bottleneck; however, analog CIM designs face challenges such as read disturbance, nonlinearity, and process-voltage-temperature (PVT) variations. Therefore, this paper presents an 8-transistor SRAM CIM macro with built-in PVT robustness to tackle these challenges. The proposed dynamic cascode SRAM bitcell utilizes stacked high- and low-Vth NMOS access devices and multilevel current-mode word-line driving to enhance read stability and achieve up to 54-fold lower bitcell current variability without requiring separate read/write ports. A subthreshold current-starved ring oscillator and a transmission-gate counter perform time-based analog-to-digital conversion of MAC results, achieving an integral nonlinearity of <0.5 LSB across PVT corners without calibration circuits. Post-layout results in TSMC 65 nm CMOS LP technology show a storage density of 241 kb/mm2 and an area efficiency of 31.32 TOPS/mm2 for 2-bit inputs and 1-bit weights. The 64×128 macro maintains functionality from 0.65 V to 1.2 V and yields <0.8% MNIST accuracy loss, demonstrating robust, energy-efficient CIM for edge AI.