Modeling of the SiO2/SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

A new analytical description of the trapped charge distribution at the semiconductor–insulator interface of 4H-SiC vertical-DMOSFET has been derived as a function of the surface potential into the channel. The model allows one to accurately calculate the electrical characteristics of the device in both subthreshold and above-threshold operations, namely, when the channel works from weak accumulation to strong inversion. The accuracy of the model has been verified by comparisons with numerical simulations and with experimental measurements of a 1.7-kV commercial device.