This paper proposes an ultra-low-power hardware architecture of a tiny machine learning (tinyML)-based conversion from Pulse Density Modulation (PDM) to Pulse Code Modulation (PCM). A hardware-aware efficient design of this conversion is essential to interface digital MEMS microphones, which outputs PDM signals, with audio processing systems, which takes PCM signals, in scenarios of in-sensor computing Keyword Spotting (KWS) applications. Neural network methods are used in a view to effectively combine the proposed converter with tinyML KWS systems, realizing an end-to-end KWS application. The proposed converter consists of a 1-D Convolutional Neural Network, which has been 8-bit quantized to reduce the computational complexity while preserving a 48 dB of Signal-to-Noise Ratio. The hardware accelerator has been implemented on a Xilinx Artix-7 FPGA, achieving a dynamic power consumption (DynP) of 182 µW, a utilization of 917 LUTs and 361 FFs. When the proposed converter is used in the KWS pipeline, the classification accuracy is 89% over 12 classes. Synthesis results in TSMC 0.13 µm CMOS report an area of 0.086 mm2 and a DynP of 837 µW, making it possible to integrate the converter into the sensor integrated circuit.

A 0.8 mW TinyML-Based PDM-to-PCM Conversion for In-Sensor KWS Applications

Vitolo P.;Liguori R.;Di Benedetto L.;Rubino A.;Licciardo G. D.
2022-01-01

Abstract

This paper proposes an ultra-low-power hardware architecture of a tiny machine learning (tinyML)-based conversion from Pulse Density Modulation (PDM) to Pulse Code Modulation (PCM). A hardware-aware efficient design of this conversion is essential to interface digital MEMS microphones, which outputs PDM signals, with audio processing systems, which takes PCM signals, in scenarios of in-sensor computing Keyword Spotting (KWS) applications. Neural network methods are used in a view to effectively combine the proposed converter with tinyML KWS systems, realizing an end-to-end KWS application. The proposed converter consists of a 1-D Convolutional Neural Network, which has been 8-bit quantized to reduce the computational complexity while preserving a 48 dB of Signal-to-Noise Ratio. The hardware accelerator has been implemented on a Xilinx Artix-7 FPGA, achieving a dynamic power consumption (DynP) of 182 µW, a utilization of 917 LUTs and 361 FFs. When the proposed converter is used in the KWS pipeline, the classification accuracy is 89% over 12 classes. Synthesis results in TSMC 0.13 µm CMOS report an area of 0.086 mm2 and a DynP of 837 µW, making it possible to integrate the converter into the sensor integrated circuit.
2022
978-3-031-26065-0
978-3-031-26066-7
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4819417
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