A DC SPICE model of a 4H-Silicon Carbide lateral n-type Metal Oxide Semiconductor Field Effect Transistors is proposed. Basing on a SPICE MOSFET Level 3 model, we introduce a novel equation of the threshold voltage, because its classic description is invalid due to the high density of traps at the oxide/semiconductor interface. Moreover, we also consider the body effects on the threshold voltage and on the channel mobility as well as the high-field effects. The accuracy of our model has been verified through the comparisons with experimental data and the relative Verilog-A BSIM4SiC model. The devices are fabricated with the 2μm CMOS process by Fraunhofer IISB and have channel length and width of 10μm. The output and trans-characteristics are for room temperature and under different bias conditions of the drain, gate and body terminals.

A DC SPICE Level 3 Model for 4H-SiC lateral NMOSFET under strong inversion conditions

Rinaldi N.;Licciardo G. D.;Di Benedetto L.;
2023-01-01

Abstract

A DC SPICE model of a 4H-Silicon Carbide lateral n-type Metal Oxide Semiconductor Field Effect Transistors is proposed. Basing on a SPICE MOSFET Level 3 model, we introduce a novel equation of the threshold voltage, because its classic description is invalid due to the high density of traps at the oxide/semiconductor interface. Moreover, we also consider the body effects on the threshold voltage and on the channel mobility as well as the high-field effects. The accuracy of our model has been verified through the comparisons with experimental data and the relative Verilog-A BSIM4SiC model. The devices are fabricated with the 2μm CMOS process by Fraunhofer IISB and have channel length and width of 10μm. The output and trans-characteristics are for room temperature and under different bias conditions of the drain, gate and body terminals.
2023
979-8-3503-0320-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4840151
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