The design of a novel, Dynamically Adaptive Accumulator (DAA) is presented. It exploits a new approach to reconfigure the fixed-point input data and multiply-accumulation results to find the optimal trade-off between accuracy and bit-width of data during calculations. The dynamic allocation of resources makes the DAA capable to extend the maximum number of accumulations before an approximation error occurs. The careful design of the DAA results in a very compact architecture and low power implementation that makes the proposed solution very suitable for the acceleration of Neural Network calculations.To validate the effectiveness of our approach, the proposed architecture have been implemented on the Xilinx Artix-7 FPGA and compared it with most-used fixed-point (fixp) and floating-point (fp) alternatives. The results show that the DAA effectively overcomes the counterparts in terms of maximum number of accumulations, area occupation, and power dissipation, presenting a reduction of 84(82)% in LUTs, 77(93)% in FFs and a 7.5× (17×) improvement in Pdyn compared to fixp(fp). The results suggest that the DAA is a promising solution for ISC ANN contexts, offering an improved resource efficiency that make it well-suited for emerging IoT and sensor applications.

Dynamically Adaptive Accumulator for in-sensor ANN Hardware Accelerators

Fasolino A.;Vitolo P.;Liguori R.;Di Benedetto L.;Rubino A.;Licciardo G. D.
2024-01-01

Abstract

The design of a novel, Dynamically Adaptive Accumulator (DAA) is presented. It exploits a new approach to reconfigure the fixed-point input data and multiply-accumulation results to find the optimal trade-off between accuracy and bit-width of data during calculations. The dynamic allocation of resources makes the DAA capable to extend the maximum number of accumulations before an approximation error occurs. The careful design of the DAA results in a very compact architecture and low power implementation that makes the proposed solution very suitable for the acceleration of Neural Network calculations.To validate the effectiveness of our approach, the proposed architecture have been implemented on the Xilinx Artix-7 FPGA and compared it with most-used fixed-point (fixp) and floating-point (fp) alternatives. The results show that the DAA effectively overcomes the counterparts in terms of maximum number of accumulations, area occupation, and power dissipation, presenting a reduction of 84(82)% in LUTs, 77(93)% in FFs and a 7.5× (17×) improvement in Pdyn compared to fixp(fp). The results suggest that the DAA is a promising solution for ISC ANN contexts, offering an improved resource efficiency that make it well-suited for emerging IoT and sensor applications.
2024
979-8-3503-3099-1
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11386/4874751
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