In this letter, a compact DC SPICE model for 4H-SiC lateral metal oxide semiconductor field effect transistors is shown both for PMOSFET and NMOSFET. It is validated through experimental comparisons by varying channel sizes, temperature in the range between 298K and 573K, and body voltage conditions. A new model of the threshold voltage is introduced in order to take into account the effects of the high interface defects density. Finally, an inverter logic gate is simulated at different temperatures and compared with experimental data and with BSIM4SiC simulation outcomes, where a maximum logic threshold voltage error of 0.85% to the experimental data is shown compared to 6.78% of BSIM4SiC.
A 4H-SiC CMOS SPICE Level 3 Model for Circuit Simulations
Rinaldi N.;Liguori R.;Rubino A.;Licciardo G. D.;Di Benedetto L.
2024
Abstract
In this letter, a compact DC SPICE model for 4H-SiC lateral metal oxide semiconductor field effect transistors is shown both for PMOSFET and NMOSFET. It is validated through experimental comparisons by varying channel sizes, temperature in the range between 298K and 573K, and body voltage conditions. A new model of the threshold voltage is introduced in order to take into account the effects of the high interface defects density. Finally, an inverter logic gate is simulated at different temperatures and compared with experimental data and with BSIM4SiC simulation outcomes, where a maximum logic threshold voltage error of 0.85% to the experimental data is shown compared to 6.78% of BSIM4SiC.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
