Uniformity and Repeatability of the Electrical Performance of 4H-SiC Lateral CMOS Devices and Circuits After Postprocessing Annealing

In this article, we propose a postprocessing annealing for 4H-silicon carbide (SiC) CMOS technology with the aim of improving the electrical characteristics of the single devices and ICs in terms of uniformity among different dies and repeatability after thermal stress. The postprocessing annealing is performed at 673 K and under different environmental conditions, i.e., ambient, vacuum, and nitrogen, whereas the electrical characteristics are measured for 4H-SiC lateral n-type and p-type metal oxide semiconductor field-effect transistors and for integrated logic gates up to 673 K and after different thermal ramps. All the postprocessing annealing conditions induce a variation in the threshold voltages for both MOSFETs, whereas the field-effect channel mobilities result almost unchanged. For example, the threshold voltage of NMOSFETs increases, reducing the current by -9.1%, and that of PMOSFETs decreases with a rise of the current of 25%, together with a reduction of the hysteresis of subthreshold characteristics, whereas the field-effect channel mobilities are unchanged. Furthermore, 4H-SiC CMOS not logic gates have a shift of the logical threshold toward higher values, very close to the ideal value and a better repeatability of transfer characteristics from room temperature up to 673 K. In a first analysis supported by theoretical models, we can ascribe the effects of the postprocessing annealing to a reduction of the concentration of border traps located in the oxide, which significantly affect the threshold voltage and the subthreshold characteristics, but barely alter the field-effect channel mobility.