Direct Digital Frequency Synthesis with Dual-slope Approach
2003 Strollo, ANTONIO GIUSEPPE MARIA; DE CARO, Davide; Napoli, Ettore; N., Petra
FPGA implementation of OpenCV compatible background identification circuit
2012 Genovese, M.; Napoli, E.
Direct Digital Frequency Synthesizers using First-Order Polynomial Chebyshev Approximation
2002 Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; DE CARO, Davide
A high-speed sense-amplifier based flip-flop
2005 DE CARO, Davide; Napoli, Ettore; Petra, Nicola; Strollo, ANTONIO GIUSEPPE MARIA
Direct Digital Frequency Synthesizers implemented on high end FPGA devices
2013 Genovese, Mariangela; Napoli, Ettore
New Design of Squarer Circuits Using Booth Encoding and Folding Techniques
2001 STROLLO A. G., M; Napoli, E; D., DE CARO
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing
1999 Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; C., Cimino
Design and Optimization of A 250nm SOI LDMOSFET
2011 G., Camuso; F., Udrea; Napoli, Ettore; X., Luo
A New Global Optimization Algorithm and Its Application to MOSFET Model Parameter Extraction
1996 Napoli, E.; Strollo, A. G. M.
Circuital implementation of deep depletion SOI power devices
2006 Napoli, Ettore; F., Udrea
He voids lifetime control compared with buffer-layer engineering for a 600V punch-through IGBT
2002 Napoli, E.; Strollo, A. G. M.; Spirito, P.; Frisina, F.; Fragapane, L.; Fagone, D.
FPGA architecture for real time video segmentation and denoising
2012 Genovese, M.; Petra, N.; De Caro, D.; Napoli, E.; Strollo, A. G. M.
True random number generator based on LFSR sampling
2003 Strollo, ANTONIO GIUSEPPE MARIA; DE CARO, Davide; N., Petra; Napoli, Ettore
Test Pattern Generator for Hybrid Testing of Combinational
2001 DE CARO, Davide; Mazzocca, Nicola; Napoli, Ettore; Saggese, G. P.; Strollo, A. G. M.
FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage
2015 Lopez, Giorgio; Napoli, Ettore; Strollo, ANTONIO GIUSEPPE MARIA
High-speed Direct Digital Frequency Synthesizers in 0.25-um CMOS
2004 Strollo, A.; DE CARO, D.; Napoli, E.; Petra, N.
Analytical models for electric field in superjunction power devices
2009 Napoli, E.
Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding
2020 Di Meo, G.; De Caro, D.; Napoli, E.; Petra, N.; Strollo, A. G. M.
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints
2015 Lopez, Giorgio; Napoli, Ettore; Meglio, Domenico; Strollo, ANTONIO GIUSEPPE MARIA
On the Use of Approximate Multipliers in LMS Adaptive Filters
2018 Esposito, Darjn; Di Meo, Gennaro; De Caro, Davide; Petra, Nicola; Napoli, Ettore; Strollo, Antonio G. M.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Direct Digital Frequency Synthesis with Dual-slope Approach | 1-gen-2003 | Strollo, ANTONIO GIUSEPPE MARIA; DE CARO, Davide; Napoli, Ettore; N., Petra | |
| FPGA implementation of OpenCV compatible background identification circuit | 1-gen-2012 | Genovese, M.; Napoli, E. | |
| Direct Digital Frequency Synthesizers using First-Order Polynomial Chebyshev Approximation | 1-gen-2002 | Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; DE CARO, Davide | |
| A high-speed sense-amplifier based flip-flop | 1-gen-2005 | DE CARO, Davide; Napoli, Ettore; Petra, Nicola; Strollo, ANTONIO GIUSEPPE MARIA | |
| Direct Digital Frequency Synthesizers implemented on high end FPGA devices | 1-gen-2013 | Genovese, Mariangela; Napoli, Ettore | |
| New Design of Squarer Circuits Using Booth Encoding and Folding Techniques | 1-gen-2001 | STROLLO A. G., M; Napoli, E; D., DE CARO | |
| A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing | 1-gen-1999 | Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; C., Cimino | |
| Design and Optimization of A 250nm SOI LDMOSFET | 1-gen-2011 | G., Camuso; F., Udrea; Napoli, Ettore; X., Luo | |
| A New Global Optimization Algorithm and Its Application to MOSFET Model Parameter Extraction | 1-gen-1996 | Napoli, E.; Strollo, A. G. M. | |
| Circuital implementation of deep depletion SOI power devices | 1-gen-2006 | Napoli, Ettore; F., Udrea | |
| He voids lifetime control compared with buffer-layer engineering for a 600V punch-through IGBT | 1-gen-2002 | Napoli, E.; Strollo, A. G. M.; Spirito, P.; Frisina, F.; Fragapane, L.; Fagone, D. | |
| FPGA architecture for real time video segmentation and denoising | 1-gen-2012 | Genovese, M.; Petra, N.; De Caro, D.; Napoli, E.; Strollo, A. G. M. | |
| True random number generator based on LFSR sampling | 1-gen-2003 | Strollo, ANTONIO GIUSEPPE MARIA; DE CARO, Davide; N., Petra; Napoli, Ettore | |
| Test Pattern Generator for Hybrid Testing of Combinational | 1-gen-2001 | DE CARO, Davide; Mazzocca, Nicola; Napoli, Ettore; Saggese, G. P.; Strollo, A. G. M. | |
| FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage | 1-gen-2015 | Lopez, Giorgio; Napoli, Ettore; Strollo, ANTONIO GIUSEPPE MARIA | |
| High-speed Direct Digital Frequency Synthesizers in 0.25-um CMOS | 1-gen-2004 | Strollo, A.; DE CARO, D.; Napoli, E.; Petra, N. | |
| Analytical models for electric field in superjunction power devices | 1-gen-2009 | Napoli, E. | |
| Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding | 1-gen-2020 | Di Meo, G.; De Caro, D.; Napoli, E.; Petra, N.; Strollo, A. G. M. | |
| An FPGA processor for real-time, fixed-point refinement of CDVS keypoints | 1-gen-2015 | Lopez, Giorgio; Napoli, Ettore; Meglio, Domenico; Strollo, ANTONIO GIUSEPPE MARIA | |
| On the Use of Approximate Multipliers in LMS Adaptive Filters | 1-gen-2018 | Esposito, Darjn; Di Meo, Gennaro; De Caro, Davide; Petra, Nicola; Napoli, Ettore; Strollo, Antonio G. M. |
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